ST10R272L - EXTERNAL BUS INTERFACE
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This extra time is required to allow the previously selected device (via demultiplexed bus) to
release the data bus, which would be available in a demultiplexed bus cycle.
9.2.4
External data bus width
The EBC can operate on 8-bit or 16-bit wide external memory/peripherals. A 16-bit data bus
uses PORT0, while an 8-bit data bus only uses P0L, the lower byte of PORT0. This saves on
address latches, bus transceivers, bus routing and memory cost on the expense of transfer
time. The EBC can control word accesses on an 8-bit data bus as well as byte accesses on
a 16-bit data bus.
Word accesses on an 8-bit data bus are automatically split into two subsequent byte
accesses, where the low byte is accessed first, then the high byte. The assembly of bytes to
words and the disassembly of words into bytes is handled by the EBC and is transparent to
the CPU and the programmer.
Byte accesses on a 16-bit data bus require that the upper and lower half of the memory
can be accessed individually. In this case the upper byte is selected with the BHE signal,
while the lower byte is selected with the A0 signal. So the two bytes of the memory can be
enabled independent from each other, or together when accessing words.
When writing bytes to an external 16-bit device, which has a single CS input, but two WR
enable inputs (for the two bytes), the EBC can directly generate these two write control
signals. This saves the external combination of the WR signal with A0 or BHE. In this case
Figure 54 Switching from demultiplexed to multiplexed bus mode
