ST10R272L - EXTERNAL BUS INTERFACE
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ALECTL0 is ‘1’ after reset to select the slowest possible bus cycle, the other ALECTLx are
‘0’ after reset.
9.3.2
Programmable memory cycle time
The ST10R272L allows the user to adjust the controller’s external bus cycles to the access
time of the respective memory or peripheral. This access time is the total time required to
move the data to the destination. It represents the period of time during which the controller’s
signals do not change.
The external bus cycles of the ST10R272L can be extended for a memory or peripherals
which cannot keep pace with the controller’s maximum speed, by introducing wait states
during the access (see figure above). During these memory cycle time wait states the CPU
is idle.
Figure 56 ALE length control
