ST10R272L - MEMORY ORGANIZATION
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3.1.2
General purpose registers
The General Purpose Registers (GPRs) use a block of 16 consecutive words in the internal
RAM. The Context Pointer (CP) register determines the base address of the currently active
register bank. This register bank may consist of up to 16 word GPRs (R0, R1, ..., R15) and/
or, up to 16 byte GPRs (RL0, RH0, ..., RL7, RH7). The 16 byte GPRs are mapped onto the
first 8 word GPRs (see table below).
In contrast to the system stack, a register bank grows from lower towards higher address
locations and occupies a maximum space of 32 bytes. The GPRs are accessed via short 2-,
4- or 8-bit addressing modes, using the Context Pointer (CP) register as base address
(independent of the current DPP register contents). Additionally, each bit in the currently
active register-bank can be accessed individually.
The ST10R272L supports fast register-bank (context) switching. Multiple register-banks can
physically exist within the internal RAM at the same time. However, only the register-bank
selected by the Context Pointer register (CP) is active at a given time. A new
active-register-bank is selected by updating the CP register. The Switch Context (SCXT)
instruction performs register-bank switching and an automatic saving of the previous
context. The number of implemented register-banks (arbitrary sizes) is only limited by the
size of the available internal RAM.
Details on using, switching and overlapping register banks are described in “SYSTEM
PROGRAMMING” on page 303.
Internal RAM Address
Byte Registers
Word Register
<CP> + 1Eh
---
R15
<CP> + 1Ch
---
R14
<CP> + 1Ah
---
R13
<CP> + 18h
---
R12
<CP> + 16h
---
R11
<CP> + 14h
---
R10
<CP> + 12h
---
R9
<CP> + 10h
---
R8
<CP> + 0Eh
RH7
RL7
R7
<CP> + 0Ch
RH6
RL6
R6
Table 4 Mapping of general purpose registers to RAM addresses
