ST10R272L - INTERRUPT AND TRAP FUNCTIONS
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6.3
Prioritizing interrupt and PEC service requests
Interrupt and PEC service requests from all sources can be enabled for arbitration and
service (if chosen), or they may be disabled.
Interrupt requests can be enabled and disabled in three ways:
•
control bits are used to switch each individual source ‘ON’ or ‘OFF’. The control bits
(xxIE) are located in the interrupt control registers. All interrupt requests may be enabled
or disabled generally by bit IEN in the PSW register. This control bit is the ‘main switch’
that determines whether a selected is selected.
Before a request can be arbitrated, its source’s enable bit and the global enable bit must
both be set.
•
The priority level automatically selects a group of interrupt requests to be
acknowledged, disregarding all other requests. The priority level of the source that wins
the arbitration is compared against the CPU’s current level. The source is only serviced
if its level is higher than the current CPU level. Changing the CPU level to a specific
value by software, blocks all requests on the same or lower level. An interrupt source
that is assigned to level 0 will be disabled and never serviced.
•
ATOMIC and EXTend instructions automatically disable all interrupt requests for the
duration of the following 1...4 instructions. This is useful e.g. for semaphore handling and
Figure 21 Mapping of PEC pointers into the internal RAM
DSTP7
00’FCFEh
SRCP7
00’FCFCh
DSTP6
00’FCFAh
SRCP6
00’FCF8h
DSTP5
00’FCF6h
SRCP5
00’FCF4h
DSTP4
00’FCF2h
SRCP4
00’FCF0h
DSTP3
00’FCEEh
SRCP3
00’FCECh
DSTP2
00’FCEAh
SRCP2
00’FCE8h
DSTP1
00’FCE6h
SRCP1
00’FCE4h
DSTP0
00’FCE2h
SRCP0
00’FCE0h
RAM
RAM
Address
Address
