ST10R272L - CENTRAL PROCESSING UNIT
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The instruction pointer IP
This register determines the 16-bit intra-segment address of the instruction in the code
segment selected by the CSP register. The IP register is not mapped into the ST10R272L’s
address space, and cannot be directly accessed by the programmer. The IP can, however,
be modified indirectly via the stack, with a return instruction.
The IP register is implicitly updated by the CPU for branch instructions and after instruction
fetch operations.
IP (---- / --)
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Reset Value: 0000h
The Code segment pointer CSP
This non-bit addressable register selects the code segment being used at run-time to access
instructions. The lower 8 bits of register CSP select one of up to 256 segments of 64 Kbytes
each, while the upper 8 bits are reserved for future use.
Code memory addresses are generated by directly extending the 16-bit content of the IP
register by the contents of the CSP register as shown in Figure 12.
In Segmented Memory Mode, the selected number of segment address bits (7...0, 3...0 or
1...0) of the CSP register is output on the segment address pins A23/A19/A17...A16 of Port
4 for all external code accesses. For Non-segmented Memory Mode or Single Chip Mode,
the content of this register is not significant because all code accesses are automatically
restricted to segment 0.
The CSP register can be read, but not written to by data operations. However, it can be
modified either directly with the JMPS and CALLS instructions, or indirectly via the stack with
Bit
Function
ip
Specifies the intra segment offset, from where the current instruction is to be fetched.
IP refers to the current segment <SEGNR>.
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4
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1
0
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15
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(r)(w)
ip
