ST10R272L - CENTRAL PROCESSING UNIT
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Timing
Instruction pipelining reduces the average instruction processing time from four to one
machine cycles. However, there are some cases, where the pipeline causes the a single
instruction processing to be extended, either by a half or by one machine cycle.
The following section gives some hints on optimizing time-critical programs, with regard to
the pipeline.
4.2
Bit-handling and bit-protection
The ST10R272L provides several bit manipulation mechanisms which manipulate software
flags within the internal RAM, control on-chip peripherals via control bits in their respective
SFRs, or control IO functions via port pins.
The instructions BSET, BCLR, BAND, BOR, BXOR, BMOV and BMOVN explicitly set or
clear specific bits. The instructions BFLDL and BFLDH manipulate up to 8 bits of a specific
byte at one time. The instructions JBC and JNBS implicitly clear or set the specified bit when
the jump is taken. The instructions JB and JNB (also conditional jump instructions that refer
to flags) evaluate the specified bit, to determine if the jump is to be taken.
Note
Bit operations on undefined bit locations will always read a bit value of ‘0’, while the
write access will not affect the respective bit location.
All instructions that manipulate single bits or bit groups internally, use a read-modify-write
sequence that accesses the whole word. This method has several consequences:
•
Bits can only be modified within the internal address areas, i.e. internal RAM and SFRs.
External locations cannot be used for bit instructions.The upper 256 bytes of the SFR
area, the ESFR area and the internal RAM are bit-addressable (refer to “MEMORY
ORGANIZATION” on page 25) i.e. those register bits located within the respective
sections can be directly manipulated using bit instructions. The other SFRs must be
accessed byte/word wise. Note: all GPRs are bit-addressable, independent of the
allocation of the register bank via the context pointer CP. Even GPRs which are allocated
to non-bit-addressable RAM locations provide this feature.
•
The read-modify-write approach may be critical with hardware-effected bits. In these
cases, the hardware may change specific bits while the read-modify-write operation is in
progress - where the writeback overwrites the new bit value generated by the hardware.
Hardware protection (see below) or special programming(see Section 4.1.4) is required .
Protected bits are not changed during the read-modify-write sequence, i.e. when hardware
sets, for example, an interrupt request flag between the read and the write of the
read-modify-write sequence. The hardware protection logic guarantees that only the
intended bit(s) is/are affected by the write-back operation. Refer to “Protected bits” on
page 23 for a summary of the protected bits implemented on this device.