ST10R272L - SYSTEM RESET
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bit ALECTL0 in register BUSCON0 is set to ‘1’
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bit ROMEN in register SYSCON will be cleared to ‘0’
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bit BYTDIS in register SYSCON is set according to the data bus width
The other bits of register BUSCON0, and the other BUSCON registers are cleared. This
default initialization selects the slowest possible external accesses using the configured bus
type. The Ready function is disabled at the end of the internal system reset.
When the internal reset has completed, the configuration of PORT0, PORT1, Port 4, Port 6
and of the BHE signal (High Byte Enable, alternate function of P3.12) depends on the bus
type which was selected during reset. When any of the external bus modes was selected
during reset, PORT0 (and PORT1) will operate in the selected bus mode. Port 4 will output
the selected number of segment address lines (all zero after reset) and Port 6 will drive the
selected number of CS lines (CS0 will be ‘0’, while the other active CS lines will be ‘1’).
When no memory accesses above 64 K are to be performed, segmentation may be
disabled.
All other pins remain in the high-impedance state until they are changed by software or
peripheral operation.
15.10
Application specific initialization routine
After the internal reset condition is removed the ST10R272L fetches the first instruction from
location 00’0000h, which is the first vector in the trap/interrupt vector table, the reset vector.
4 words (locations 00’0000h through 00’0007h) are provided in this table to start the
initialization after reset. As a rule, this location holds a branch instruction to the actual
initialization routine that may be located anywhere in the address space.
After reset, it may be desirable to reconfigure the external bus characteristics, because the
SYSCON register is initialized during reset to the slowest possible memory configuration.
To decrease the number of instructions required to initialize the ST10R272L, each peripheral
is programmed to a default configuration upon reset, but is disabled from operation. These
default configurations can be found in the descriptions of the individual peripherals.
During the software design phase, portions of the internal memory space must be assigned
to register banks and system stack. When initializing the stack pointer (SP) and the context
pointer (CP), it must be ensured that these registers are initialized before any GPR or stack
operation is performed. This includes interrupt processing, which is disabled upon
completion of the internal reset, and should remain disabled until the SP is initialized.
Note
Traps (incl. NMI) may occur, even though the interrupt system is still disabled.
In addition, the stack overflow (STKOV) and the stack underflow (STKUN) registers should
be initialized. After reset, the CP, SP, and STKUN registers all contain the same reset value
00’FC00h, while the STKOV register contains 00’FA00h. With the default reset initialization,