ST10R272L - SYNCHRONOUS SERIAL PORT
251/320
XP1IC (F18Eh)
ESFR
Reset Value: - - 00h
Note
Refer to “Interrupt control registers” on page 86 for an explanation of the control
fields.
13.2.11 SSP input/output pins
The SSP is connected to the external world by the following four signals on Port 4:
Note
These SSP signals are only available on the Port 4 pins, if Port 4 is not
programmed to output all 8 segment address lines. Select 0, 2 or 4 segment
address lines (at start-up configuration during reset) if the SSP is to be used.
13.2.12 Accessing the on-chip SSP
The SSP is accessed like an external memory or peripheral. That means that the registers of
the SSP can be read and written using 16-bit or 8-bit direct or indirect MEM addressing
modes. Since the XBUS, to witch the SSP is connected, also represents the external bus,
SSP accesses follow the same rules and procedures as accesses to the external bus. SSP
accesses cannot be executed in parallel to external instruction fetches or data read/writes,
but are arbitrated and inserted into the external bus access stream.
However, the on-chip SSP is accessed via the 16-bit demultiplexed bus mode exclusively.
This provides the user the fastest access to the SSP registers.
When accessing the on-chip SSP, the bus has to be switched to the appropriate bus mode
within the SSP address range. This is done via a specific register-pair, XBCON1 and
XADRS1, which is similar to the BUSCONx/ADDRSELx register-pairs. With the XBCON1
register (XBUS Bus Configuration Register 1), the bus mode, number of waitstates, etc., for
accessing the SSP are controlled. The XADRS1 register (XBUS Address Select Register 1)
SSP Signal
Port Pin
Function
SSPCLK
P4.7
Clock Line of the SSP.
SSPDAT
P4.6
Data Input/Output Line of the SSP.
SSPCE0
P4.5
Chip Enable Line 0 of the SSP.
SSPCE1
P4.4
Chip Enable Line 1 of the SSP.
Table 42 SSP input/output pins
5
4
3
2
1
0
11
10
9
8
7
6
15
14
13
12
rw
rw
rw
XP1IR XP1IE
-
-
-
-
-
-
-
-
ILVL
rw
GLVL
