ST10R272L - EXTERNAL BUS INTERFACE
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The chip select signals can be used for four operating modes, selected via bits CSWENx
and CSRENx in the respective BUSCONx register.
Address chip select signals remain active for the whole external bus cycle. An address
chip select becomes active with the falling edge of ALE and becomes inactive with the falling
edge of ALE of an external bus cycle that accesses a different address area. No spikes will
be generated on the chip select lines.
Read or write chip select signals remain active only as long as the associated control
signal (RD or WR) is active. This also includes the programmable read/write delay. Read
chip select is only activated for read cycles, write chip select is only activated for write cycles,
read/write chip select is activated for both read and write cycles (write cycles are assumed,
if any of the signals WRH or WRL gets active). These modes save external glue logic, when
accessing external devices like latches or drivers that only provide a single enable input.
CS0 provides an address chip select directly after reset (except for single chip mode) when
the first instruction is fetched.
Internal pullup devices hold the selected CS lines high during reset. After the end of a reset
sequence the pullup devices are switched off and the pin drivers control the pin levels on the
selected CS lines. Not selected CS lines will enter the high-impedance state and are
available for general purpose I/O.
The pullup devices are also active during bus hold, while HLDA is active and the respective
pin is switched to push/pull mode. Open drain outputs will float during bus hold. In this case
external pullup devices are required or the new bus master is responsible for driving
appropriate levels on the CS lines.
9.2.8
Segment address versus chip select
The external bus interface of the ST10R272L supports many configurations for the external
memory. By increasing the number of segment address lines the ST10R272L can address a
linear address space of 256 KByte, 1 MByte or 16 MByte. This allows to implement a large
sequential memory area, and also allows to access a great number of external devices,
using an external decoder. By increasing the number of CS lines the ST10R272L can
CSWENx
CSRENx
Chip Select Mode
0
0
Address Chip Select (Default after Reset)
0
1
Read Chip Select
1
0
Write Chip Select
1
1
Read/Write Chip Select
Table 27 Chip select mode
