ST10R272L - EXTERNAL BUS INTERFACE
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access memory banks or peripherals without external glue logic. These two features may be
combined to optimize the overall system performance. Enabling 4 segment address lines
and 5 chip select lines e.g. allows to access five memory banks of 1 MByte each. So the
available address space is 5 MByte (without glue logic).
Note
Bit SGTDIS of SYSCON register defines whether the CSP register is saved during
interrupt entry (segmentation active) or not (segmentation disabled).
9.3
Programmable bus characteristics
Important timing characteristics of the external bus interface (Memory Cycle Time, Memory
Tri-State Time, Length of ALE and Read Write Delay) have been made programmable to al-
low the user the use of a wide range of different types of memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs AD-
DRSELx / BUSCONx) which allow to access different resources with different bus character-
istics. These address windows are arranged hierarchically where BUSCON4 overrides
BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by
these 4 address windows are controlled by BUSCON0. Up to 5 external CS signals (4 win-
dows plus default) can be generated in order to save external glue logic. Access to very slow
memories is supported via a particular ‘Ready’ function.
The following parameters of an external bus cycle are programmable:
ALE control:
Defines the ALE signal length and the address hold time
after its falling edge.
Memory cycle time:
Defines the allowable access time (extendable wit h 1...15
waitstates).
Memory tri-state time:
Defines the time for a data driver to float (extendable with 1
waitstate).
Read/write delay time:
Defines when a command is activated after falling edge of
ALE.
READY:
Polarity is programmable.
Chip select timing
control:
Adjusts the position of the CSx lines.
Table 28 ProgrammableEBI parameters
