ST10R272L - SYNCHRONOUS SERIAL PORT
247/320
Performing a read operation
If the SPRW bit in register SSPCON0 is set, a read operation is selected. During a read
operation, first information (command or address information) is transferred from the CPU
(master) to the slave peripheral. Then the transfer direction is switched, and information is
transferred from the slave to the master. As for the write operation, the transmit buffers
SSPTB2...SSPTB0 are written by the CPU with the information data to be first transferred.
Writing to SSPTB0 will start the transfer. The following figure shows the basic waveforms for
a read operation of the SSP.
For the first part of a read operation (transfer of SSPTBx from master to slave), the same
rules as for the write operation are applied concerning the relation between the transfer
length and writes in the Transmit Buffers.After writing to SSPTB0, first the content of the
transmit buffers are shifted out. Then the data line SSPDAT is switched to input
(high-impedance). After a gap of one bit clock, the data present at the SSPDAT pin is latched
in with the next 8 clock edges. When the last bit is clocked in, the chip enable line is
deactivated one half bit time later.
13.2.7 Chip enable lines
Two chip enable lines are provided by the SSP which are automatically activated at the
beginning of a transfer and deactivated again after the transfer is completed. As shown in
the previous figures, activation of a chip enable line always begins one half bit time before
the first data bit is output at the SSPDAT pin, and the deactivation (except for continuous
transfers) is performed one half bit time after the last bit of the transfer has been completely
transmitted/received.
Figure 102 Read operation waveforms
SSPCLK
SSPCEx
SSPDAT
23/15/7
6
0
0.5
0
1
7
BT
0.5
BT
0.5
BT
1 Bit
Time
Data driven by master
Data driven by slave
