ST10R272L - GENERAL PURPOSE TIMER UNITS
192/320
11.1.1 GPT1 core timer T3
The core timer T3 is configured and controlled by its bit addressable control register T3CON.
T3CON (FF42h / A1h)
SFR
Reset Value: 0000h
Bit
Function
T3I
Timer 3 Input Selection
Depends on the operating mode, see respective sections.
T3M
Timer 3 Mode Control (Basic Operating Mode)
0 0 0:
Timer Mode
0 0 1:
Counter Mode
0 1 0:
Gated Timer with Gate active low
0 1 1:
Gated Timer with Gate active high
1 X X:
Reserved. Do not use this combination.
T3R
Timer 3 Run Bit
T3R = ‘0’:
Timer / Counter 3 stops
T3R = ‘1’:
Timer / Counter 3 runs
T3UD
Timer 3 Up / Down Control
1
1.
For bits T3UD and T3UDE refer to Table 31 GPT1 core timer T3 count direction control
below.
T3UDE
Timer 3 External Up/Down Enable
1
T3OE
Alternate Output Function Enable
T3OE =’0’
Alternate Output Function Disable
T3OE = ‘1’:
Alternate Output Function Enabled
T3OTL
Timer 3 Output Toggle Latch
Toggles on each overflow / underflow of T3. Can be set or reset by software.
5
4
3
2
1
0
11
10
9
8
7
6
15
14
13
12
rw
rw
-
rw
rw
rw
rw
rw
-
-
-
-
T3R
T3UD
T3OE
-
-
-
-
-
T3
OTL
T3
UDE
T3M
T3I
