ST10R272L - ARCHITECTURAL OVERVIEW
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A set of consistent flags is automatically updated in the PSW after each arithmetic, logical,
shift, or movement operation. These flags cause branching on specific conditions.
User-specifiable branch tests give support for signed and unsigned arithmetic. These flags
are preserved automatically by the CPU on entry into an interrupt or trap routine. All targets
for branch calculations are computed in the central ALU.
A 16-bit barrel shifter provides multiple bit shifts in a single cycle. Rotates and arithmetic
shifts are also supported.
2.1.3
Extended bit processing and peripheral control
A large number of instructions have been dedicated to bit processing, to provide efficient
control and testing of peripherals while enhancing data manipulation. These instructions
provide direct access to two operands in the bit-addressable space, without using temporary
flags.
The same logical instructions that are available for words and bytes, are also supported for
bits. A peripheral control bit can be compared and modified in one instruction. Multiple bit
shift instructions avoid long instruction streams of single bit shift operations. These are also
performed in a single machine cycle.
Bit field instructions can modify multiple bits from one operand, in a single instruction.
2.1.4
High performance branch, call, and loop processing
Branch instructions only require one extra machine cycle when a branch is taken, because
the target address is pre-calculated while decoding the instruction. To decrease loop
execution overhead, three enhancements have been provided:
•
Single cycle branch execution is perfomed after the first iteration of a loop. Therefore,
only one machine cycle is lost during the execution of the entire loop. In loops which fall
through on completion, no machine cycles are lost when exiting the loop. No special
instructions are required to perform loops, and loops are automatically detected during
execution of branch instructions.
•
End-of-table detection avoids the use of two compare instructions embedded in loops.
The lowest negative number is placed at the end of the table and branching is specified
if neither this value nor the compared value have been found. The loop is terminated if
either condition is met. The terminating condition can then be tested.
•
The third loop enhancement provides a more flexible solution than the Decrement and
Skip on Zero instruction found in other microcontrollers. Through the use of Compare
and Increment or Decrement instructions, the user can make comparisons to any value.
This allows loop counters to cover any range, which is useful in table searching.
The system state is automatically saved on the internal system stack . Instructions are not
required to preserve state upon entry and exit of interrupt or trap routines. Call instructions