ST10R272L - GENERAL PURPOSE TIMER UNITS
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The incremental encoder can be connected directly to the ST10R272L without external
interface logic. However, in a standard system comparators are employed to convert the
encoder’s differential outputs (e.g. A, A) to digital signals (e.g. A). this greatly increases
noise immunity.
Note
The third encoder output Top0 which indicates the mechanical zero position, may
be connected to an external interrupt input and trigger a reset timer T3 (e.g.via PEC
transfer from ZEROS).
For incremental interface operation the following conditions must be met
•
Bitfield T3M must be ‘110
B
’
•
Both pins T3IN and T3EUD must be configured as input, i.e. the respective direction
control bits must be ‘0’.
•
Bit T3EUD must be ‘1’ to enable automatic direction control.
The maximum allowed input frequency in incremental interface mode is f
CPU
/16. To ensure
correct recognition of the transition of any input signal, its level should be held high or low for
at least 8 CPU clock cycles.
Figure 74 Encoder - ST10R272L connection
T3input
T3input
Interrupt
S
T
10
X
1
67
A
B
T0
A
A
B
B
T0
T0
E
NCO
DE
R
Signal Conditioning
