ST10R272L - ARCHITECTURAL OVERVIEW
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For applications which require less than 16MBytes of external memory space, the address
space can be restricted to 1MByte, 256KByte or to 64KByte. Port 4 outputs four, two or no
address lines. If an address space of 16MBytes is used, Port 4 outputs all 8 address lines.
The on-chip XBUS is an internal representation of the external bus. It is used to access
integrated application-specific peripherals/modules in the same way as external
components. It provides a defined interface for customized peripherals.
2.3
System clock generator
The on-chip clock generator provides the basic clock signal that controls the activities of the
controller hardware. Its oscillator can run with an external crystal and appropriate oscillator
circuitry (refer to “DEDICATED PINS” on page 143) or can be driven by an external
oscillator. The oscillator can directly feed the external clock signal to the controller hardware
(through buffers) and divides the external clock frequency by 2, or feeds an on-chip phase
locked loop (PLL) which multiplies the input frequency by a selectable factor F. The resulting
internal clock signal is referred to as the ‘CPU clock’. Two separate clock signals are
generated for the CPU and the peripherals. While the CPU clock is stopped during idle
mode, the peripheral clock keeps running. Both clocks are switched off when power-down
mode is entered.
The on-chip PLL circuit allows operation of the ST10R272L on a low frequency external
clock while still providing maximum performance. The PLL multiplies the external clock
frequency by a selectable factor of 1:F and generates a CPU clock signal with 50% duty
cycle. The PLL also provides fail safe mechanisms which detect frequency deviations and
the execution of emergency actions in case of an external clock failure. (Refer to
“WATCHDOG TIMER” on page 255.)
