ST10R272L - PARALLEL PORTS
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DP6 (FFCEh / E7h)
SFR
Reset Value: - - 00h
ODP6 (F1CEh / E7h)
ESFR
Reset Value: - - 00h
7.7.1
Alternate functions of Port 6
A programmable number of chip select signals (CS4...CS0) derived from the bus control
registers (BUSCON4...BUSCON0) can be output on 5 pins of Port 6. The other 3 pins may
be used for bus arbitration to accommodate additional masters in a ST10R272L system.
The number of chip select signals is selected via PORT0 during reset. The selected value
can be read from bitfield CSSEL in register RP0H (read only) e.g. in order to check the
configuration during run time.
Bit
Function
DP6.y
Port direction register DP6 bit y
DP6.y = 0: Port line P6.y is an input (high-impedance)
DP6.y = 1: Port line P6.y is an output
Bit
Function
ODP6.y
Port 6 Open Drain control register bit y
ODP6.y = 0: Port line P6.y output driver in push/pull mode
ODP6.y = 1: Port line P6.y output driver in open drain mode
5
4
3
2
1
0
11
10
9
8
7
6
15
14
13
12
rw
rw
rw
rw
rw
rw
-
-
-
-
rw
rw
-
-
-
-
DP6.0
DP6.1
DP6.2
DP6.3
DP6.4
DP6.5
DP6.6
DP6.7
5
4
3
2
1
0
11
10
9
8
7
6
15
14
13
12
rw
rw
rw
rw
rw
rw
-
-
-
-
rw
rw
-
-
-
-
ODP6
.7
ODP6
.6
ODP6
.5
ODP6
.4
ODP6
.3
ODP6
.2
ODP6
.1
ODP6
.0