ST10R272L - ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE
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Pin TXD0/P3.10 must be configured for alternate data output, i.e. P3.10=’1’ and DP3.10=’1’,
in order to provide the shift clock. Pin RXD0/P3.11 must also be configured for output
(P3.11=’1’ and DP3.11=’1’) during transmission.
Synchronous reception is initiated by setting bit S0REN=’1’. If bit S0R=1, the data applied
at pin RXD0 are clocked into the receive shift register synchronous to the clock which is
output at pin TXD0. After the 8th bit has been shifted in, the content of the receive shift
register is transferred to the receive data buffer S0RBUF, the receive interrupt request flag
S0RIR is set, the receiver enable bit S0REN is reset, and serial data reception stops.
Pin TXD0/P3.10 must be configured for alternate data output, i.e. P3.10=’1’ and DP3.10=’1’,
in order to provide the shift clock. Pin RXD0/P3.11 must be configured as alternate data
input (DP3.11=’0’).
Synchronous reception is stopped by clearing bit S0REN. A currently received byte is
completed including the generation of the receive interrupt request and an error interrupt
request, if appropriate. Writing to the transmit buffer register while a reception is in progress
has no effect on reception and will not start a transmission.
If a previously received byte has not been read out of the receive buffer register at the time
the reception of the next byte is complete, both the error interrupt request flag S0EIR and the
overrun error status flag S0OE will be set, provided the overrun check has been enabled by
bit S0OEN.
12.3
Hardware error detection capabilities
To improve the safety of serial data exchange, the serial channel ASC0 provides an error
interrupt request flag, which indicates the presence of an error, and three (selectable) error
status flags in register S0CON, which indicate which error has been detected during
reception. Upon completion of a reception, the error interrupt request flag S0EIR will be set
simultaneously with the receive interrupt request flag S0RIR, if one or more of the following
conditions are met:
•
If the framing error detection enable bit S0FEN is set and any of the expected stop bits is
not high, the framing error flag S0FE is set, indicating that the error interrupt request is
due to a framing error (Asynchronous mode only).
•
If the parity error detection enable bit S0PEN is set in the modes where a parity bit is
received, and the parity check on the received data bits proves false, the parity error flag
S0PE is set, indicating that the error interrupt request is due to a parity error
(Asynchronous mode only).
•
If the overrun error detection enable bit S0OEN is set and the last character received
was not read out of the receive buffer by software or PEC transfer at the time the
reception of a new frame is complete, the overrun error flag S0OE is set indicating that
