ST10R272L - SYSTEM RESET
262/320
.
1
RSTIN assertion can be released there.
2
If during the reset condition (RSTIN low), RPD/Vpp voltage drops below the threshold
voltage (about 2.5V for 5V operation and 2.0V for 3.3V operation), the asynchronous
reset is then immediately entered.
RSTIN rising edge to internal latch of Port0 is 3CPU clock cycles if the PLL is bypassed and
the prescaler is on (f
CPU
= f
XTAL
/ 2), else it is 4 CPU clock cycles.
Figure 109 Synchronous warm reset:
external low pulse on RSTIN shorter than reset sequence
CPU Clock
RSTIN
Internal
Reset Configuration
INST #1
PORT 0
RSTOUT
ALE
6 CPU clock max
512 CPU clock
RPD/Vpp
internally pulled low
Reset
Signal
Latching point of Port0
for system start-up configuration
200 µA Discharge
2)
RPD/Vpp >2V 3.3Voperation, >2.5V 5Voperation:
not entered.
1)
2 CPU clock min
3 or 4 CPU clock 3)
Asynchronous Reset
