ST10R272L - CENTRAL PROCESSING UNIT
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external memory accesses performed by the EBC, due to the predefined priority of external
memory accesses:
1st
Write Data
2nd
Fetch Code
3rd
Read Data
Controlling interrupts
Software modifications (implicit or explicit) of the PSW are done in the EXECUTE phase of
the respective instructions. However, to maintain fast interrupt responses, the current
interrupt-prioritization round does not consider these changes - i.e. an interrupt request may
be acknowledged after the instruction that disables interrupts via IEN or ILVL, or after the
following instructions. Therefore, time critical instruction sequences should not begin directly
after the instruction disabling interrupts, as shown in the following example:
Note
A delay of one instruction also applies to the enabling of the interrupt system, i.e. no
interrupt requests are acknowledged until the instruction following the enabling
instruction is FETCHED.
Initialization of port pins
Port pins direction modifications (input or output) become effective, only after the instruction
following the modifying instruction. As bit instructions (BSET, BCLR) use internal
read-modify-write sequences (accessing the whole port), instructions modifying the port
INT_OFF:
BCLR
IEN
;globally disable interrupts
I
N-1
;non-critical instruction
CRIT_1ST
:
I
N
;begin of uninterruptable critical sequence
. . .
CRIT_LAST
:
I
N+x
;end of uninterruptable critical sequence
INT_ON:
BSET
IEN
;globally re-enable interrupts
