ST10R272L - ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE
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ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE
The asynchronous/synchronous serial interface ASC0 provides serial communication
between the ST10R272L and other microcontrollers, microprocessors or external
peripherals.
A dedicated baud rate generator sets up all standard baud rates without oscillator tuning. 3
separate interrupt vectors are provided for transmission, reception and erroneous reception.
In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a
start bit and terminated by one or two stop bits. For multiprocessor communication, there is
a mechanism to distinguish address from data bytes (8-bit data + wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift
clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back
option is available for testing purposes.
A number of optional hardware error detection capabilities increase the reliability of data
transfers. A parity bit can automatically be generated on transmission or be checked on
reception. Framing error detection recognizes data frames with missing stop bits. An overrun
error will be generated, if the last character received has not been read out of the receive
buffer register by the time a new character is received.
The operating mode of the serial channel ASC0 is controlled by its bit addressable control
register S0CON. This register contains control bits for mode and error check selection, and
status flags for error identification.
A transmission is started by writing to the (write-only) transmit buffer register S0TBUF (by an
instruction or a PEC data transfer). Only the number of data bits which is determined by the
selected operating mode will actually be transmitted, i.e. bits written to positions 9 through
15 of register S0TBUF are always insignificant. After a transmission has been completed,
the transmit buffer register is cleared to 0000h.
Data transmission is double-buffered, so a new character may be written to the transmit
buffer register, before the transmission of the previous character is complete. This allows to
send characters back-to-back without gaps.
Data reception is enabled by the Receiver Enable Bit S0REN. After reception of a character
has been completed, the received data and, if provided by the selected operating mode, the
received parity bit can be read from the (read-only) Receive Buffer register S0RBUF. Bits in
the upper half of S0RBUF which are not valid in the selected operating mode will be read as
zeros.
Data reception is double-buffered, so that reception of a second character may already
begin before the previously received character has been read out of the receive buffer
register. In all modes, receive buffer overrun error detection can be selected through bit
S0OEN. When enabled, the overrun error status flag S0OE and the error interrupt request
flag S0EIR will be set when the receive buffer register has not been read by the time
reception of a second character is complete. The previously received character in the
receive buffer is overwritten.
