ST10R272L - SYNCHRONOUS SERIAL PORT
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The clock control adapts transmit and receive behavior of the SSP to a variety of serial
interfaces. A specific clock edge (rising or falling) is used to shift out transmit data, while the
other clock edge is used to latch in receive data. Bit SSPKE selects the leading edge or the
trailing edge for each function. Bit SSPKP selects the level of the clock line in the idle state.
So for an idle-high clock the leading edge is a falling one, a 1-to-0 transition. The figure
below is a summary.
13.2.2 SSP Control Register 1 - SSPCON1
This register contains all bits which are required to configure the output lines of the SSP. It
contains control bits which are normally written once during the initialization of the system.
SSPBSY
SSP Busy Flag
0:
SSP is idle
1:
SSP is busy.
The Busy flag is set with the first write into one of the transmit buffers. It is automati-
cally cleared after the last bit has been transferred and selected chip select line is
switched inactive.
Figure 99 Serial clock phase and polarity options
Bit
Function
Serial Clock
SSPCLK
Data driven by CPU
Data driven by slave
Latch Data
Shift Data
SSP
0
0
0
1
1
0
1
1
CKE
SSPDAT
SSP
CKP
SSPCEx