ST10R272L - ARCHITECTURAL OVERVIEW
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2.4.4 Reserved
bits
Some SFRs are ’reserved’. Never write ’1’s to reserved bits. These bits are not currently
implemented and may be used in future products. The active state for these functions will be
'1', and the inactive state will be '0'. Therefore, writing only ‘0’s to reserved locations give
upgradability of current software to future devices. Read accesses to reserved bits return
‘0’s.
2.4.5
Parallel ports
The ST10R272L has up to 77 I/O lines, organized into six input/output ports and one input
port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise)
programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional
ports, which are switched to high impedance state when configured as inputs. The output
drivers of three I/O ports can be configured (pin by pin) for push/pull operation, or via the
control registers for open-drain operation. During internal reset, all port pins are configured
as inputs.
All port lines have associated, programmable, alternate, input or output functions. PORT0
and PORT1 may be used as address and data lines for external memory access. Port 4
outputs the additional segment address bits A23/19/17...A16 in systems where
segmentation is enabled to access more than 64 KBytes of memory. Port 6 provides optional
bus-arbitration signals (BREQ, HLDA, HOLD) and chip-select signals. Port 3 includes
alternate functions of timers, serial interfaces, the optional bus control signal BHE and the
system clock output (CLKOUT). Port 5 is used for timer control signals. All port lines that are
not used for these alternate functions may be used as general purpose I/O lines.
2.4.6
Serial channels
Serial communication with other microcontrollers, processors, terminals or external
peripheral components is provided by two serial interfaces - an Asynchronous/synchronous
Serial Channel (ASC0) and a Synchronous Serial Port (SSP).
ASCO supports full-duplex asynchronous communication. A dedicated baud rate generator
sets up standard baud rates without oscillator tuning. For transmission, reception, and
erroneous reception, 3 separate interrupt vectors are provided for ASC0. In asynchronous
mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and
terminated by one or two stop bits. There is a multiprocessor communication mechanism to
distinguish address from data bytes (8-bit data + wake-up bit mode). In synchronous mode,
the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is
generated by the ASC0.
The SSP can be configured to interface with serially-linked peripheral components. There is
one general interrupt vector for the SSP.
