ST10R272L - PWM MODULE
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Note
The output of the PWM module is EXORed with the output of the port output latch
(P7.3). After reset, this latch is cleared, so the PWM signal is directly driven to the
port pin. By setting the port output latch to ‘1’, the PWM signal is inverted (XORed
with ‘1’) before being driven to the port pin. The descriptions below refer to the
standard case after reset, i.e. direct driving.
10.1.1 Mode 0 - standard PWM generation (edge aligned PWM)
Mode 0 is selected by clearing bit PM3 in register PWMCON1 to ‘0’. In this mode, the PWM
timer PT3 is always counting up until it reaches the value in the period register PP3. On the
next count pulse, the timer is reset to 0000h and continues counting up with subsequent
count pulses. The PWM output signal is switched to a high level when the timer contents are
equal to or greater than the contents of the pulse width shadow register. The signal is
switched back to a low level when the timer is reset to 0000h, i.e. below the pulse width
shadow register. The period of the resulting PWM signal is determine by the value of the
PP3 register plus 1, counted in units of the timer resolution.
PWM
Period Mode
0 = [PP3] + 1
The duty cycle of the PWM output signal is controlled by the value in the pulse width shadow
register. This mechanism allows to select duty cycles from 0% to 100%, including the
boundaries. For a PW3 value of 0000h, the output will remain at a high level, representing a
duty cycle of 100%. For a PW3 value higher than the value in the period register PP3, the
output will remain at a low level, which corresponds to a duty cycle of 0%.
Figure 65 illustrates the operation and output waveforms of the PWM channel in Mode 0 for
different values in the pulse width register PW3. This mode is referred to as Edge Aligned
PWM, because the value in the pulse width (shadow) register only affects the positive edge