ST10R272L - SYSTEM RESET
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for the 512 CPU clock cycles of the internal reset sequence. After the reset sequence has
been completed, the RSTIN input is sampled. When the reset input signal is active at that
time, the internal reset signal is prolonged until RSTIN gets inactive, but the reset sequence
is not re-triggered.
During reset, internal pullup devices are active on the PORT0 lines, so that external
pulldown devices can be used to defined system start-up configuration. The values of
PORT0 lines are latched when RSTIN is internally latched high.
15.5.2 RESET output pin
The RSTOUT pin is dedicated to generate a reset signal for the system components besides
the controller itself. RSTOUT will be driven active (low) at the begin of any reset sequence
(triggered by hardware, the SRST instruction or a watchdog timer overflow). RSTOUT stays
active (low) beyond the end of the internal reset sequence until the protected EINIT (End of
Initialization) instruction is executed (see figure above). This allows to completely configure
the controller including its on-chip peripheral units before releasing the reset signal for the
external peripherals of the system.
15.6
Watchdog timer operation after reset
The watchdog timer starts running after the internal reset has completed. It will be clocked
with the internal system clock divided by 2, and its default reload value is 00h, so a watchdog
timer overflow will occur 131072 CPU clock cycles after completion of the internal reset,
unless it is disabled, serviced or reprogrammed meanwhile. When the system reset was
caused by a watchdog timer overflow, the WDTR (Watchdog Timer Reset Indication) flag in
register WDTCON will be set to ’1’. This indicates the cause of the internal reset to the
software initialization routine. WDTR is reset to ’0’ by an external hardware reset or by
servicing the watchdog timer. After the internal reset has completed, the operation of the
watchdog timer can be disabled by the DISWDT (Disable Watchdog Timer) instruction. This
instruction has been implemented as a protected instruction. For further security, its
execution is only enabled in the time period after a reset until either the SRVWDT (Service
Watchdog Timer) or the EINIT instruction has been executed. Thereafter the DISWDT
instruction will have no effect.
15.7
Registers reset values
During the reset sequence the registers are preset with a default value. Most SFRs,
including system registers and peripheral control and data registers, are cleared to zero, so
all peripherals and the interrupt system are off or idle after reset. A few exceptions to this
rule provide a first pre-initialization, which is either fixed or controlled by input pins.
DPP1:
0001h (points to data page 1)
DPP2:
0002h (points to data page 2)