ST10R272L - PWM MODULE
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PWMIC (F17Eh / BFh)
ESFR
Reset Value: - - 00h
Note
Refer to “Interrupt control registers” on page 86 for an explanation of the control
fields.
The channel interrupt request flags PIR3 (in register PWMCON0) will not be
automatically cleared by hardware upon entry into the interrupt service routine, so
they must be cleared by software. The module interrupt request flag PWMIR is
cleared by hardware upon entry into the interrupt service routine, regardless of how
many channel interrupts were active. However, it will be set again if during
execution of the service routine a new channel interrupt request is generated.
10.4
PWM output signals
In the ST10R272L, the output signal of the PWM channel 3 (POUT3) is alternate output
function on Port 7 pin 3 (P7.3). The output signal of PWM channel 3 is enabled by control bit
PEN3 in register PWMCON1.
The PWM signal is EXORed with the respective port latch outputs before being driven to the
port pin. This allows to drive the PWM signal directly to the port pin (P7.3=’0’) or drive the
inverted PWM signal (P7.3=’1’).
5
4
3
2
1
0
11
10
9
8
7
6
15
14
13
12
rw
rw
-
-
-
-
rw
rw
-
-
-
-
PWM
IE
PWM
IR
GLVL
ILVL
