ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC)
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For the CoMACM class of instruction, Parallel Data Move mechanism is implemented. This
class of instruction is only available with double indirect addressing mode. Parallel Data
Move allows the operand pointed by IDX
i
to be moved to a new location in parallel with the
MAC operation. The write-back address of Parallel Data Move is calculated depending on
the post-modification of IDX
i
. It is obtained by the reverse operation than the one used to
calculate the new value of IDX
i
. The following table shows these rules.
“[Rw
n
⊗
]” stands for
[Rwn]
(Rwn)
←
(Rwn) (no-op)
[Rwn
+
]
(Rwn)
←
(Rwn) +2 (n=0-15)
[Rwn-]
(Rwn)
←
(Rwn) -2 (k=0-15)
[Rwn
+
QRj]
(Rwn)
←
(Rwn) + (QRj) (n=0-15;j =0,1)
[Rwn - QRj]
(Rwn)
←
(Rwn) - (QRj) (n=0-15; j =0,1)
Instruction
Writeback Address
CoMACM [IDX
i
+],...
<IDX
i
-2>
CoMACM [IDX
i
-],...
<IDX
i
+2>
CoMACM [IDX
i
+QX
j
],...
<IDX
i
-QX
j
>
CoMACM [IDX
i
-QX
j
],...
<IDX
i
+QX
j
>
Table 9 Parallel data move addressing
Symbol
Mnemonic
Address Pointer Operation
Table 8 Pointer post-modification combinations for IDXi and Rwn (Continued)
