ST10R272L - INTERRUPT AND TRAP FUNCTIONS
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When internal hold conditions between instruction pairs ‘N-2/N-1’ or ‘N-1/N’ occur, or
instruction N explicitly writes to the PSW or SP, the minimum interrupt response time may be
extended by 1 CPU clock.
Where instruction N reads the PSW, and instruction N-1 has an effect on the condition flags,
the interrupt response time may be extended by 2 CPU clock cycles.
Any reference to external locations increases the interrupt response time due to pipeline
related access priorities. The following conditions have to be considered:
•
Instruction fetch from an external location
•
Operand read from an external location
•
Result write-back to an external location
Depending on where the instruction source and destination operands are located, there are
a number of combinations. Note, however, that only access conflicts contribute to the delay.
The following examples illustrate these delays:
•
The worst case interrupt response time including external accesses occur when
instructions N, N+1 and N+2 are executed out of external memory, instructions N-1 and
N require external operand read accesses, instructions N-3 through N write back
external operands, and the interrupt vector points to an external location. In this case,
the interrupt response time is the time to perform 9 word bus-accesses, because
instruction I1 cannot be fetched via the external bus until all write, fetch and read
requests of preceding instructions in the pipeline are terminated.
Figure 23 Pipeline diagram for interrupt response time
Pipeline Stage
Cycle 1
Cycle 2
Cycle 3
Cycle 4
FETCH
N
N + 1
N + 2
I1
DECODE
N - 1
N
TRAP (1)
TRAP (2)
EXECUTE
N - 2
N - 1
N
TRAP
WRITEBACK
N - 3
N - 2
N - 1
N
Interrupt Response Time
1
0
IR-Flag
