PWMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4003_318A Master Control 2 Register (PWMA_MCTRL2)
16
R/W
0000h
4003_318C Fault Control Register (PWMA_FCTRL)
16
R/W
0000h
4003_318E Fault Status Register (PWMA_FSTS)
16
R/W
0000h
4003_3190 Fault Filter Register (PWMA_FFILT)
16
R/W
0000h
4003_3192 Fault Test Register (PWMA_FTST)
16
R/W
0000h
4003_3194 Fault Control 2 Register (PWMA_FCTRL2)
16
R/W
0000h
37.4.1 Counter Register (PWMA_SMnCNT)
This read-only register displays the state of the signed 16-bit submodule counter. This
register is not byte accessible.
Address: 4003_3000h base + 0h (96d × i), where i=0d to 3d
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWMA_SMnCNT field descriptions
Field
Description
CNT
Counter Register Bits
37.4.2 Initial Count Register (PWMA_SMnINIT)
The 16-bit signed value in this buffered, read/write register defines the initial count value
for the PWM in PWM clock periods. This is the value loaded into the submodule counter
when local sync, master sync, or master reload is asserted (based on the value of
CTRL2[INIT_SEL]) or when CTRL2[FORCE] is asserted and force init is enabled. For
PWM operation, the buffered contents of this register are loaded into the counter at the
start of every PWM cycle. This register is not byte accessible.
Memory Map and Registers
KV4x Reference Manual, Rev. 2, 02/2015
780
Preliminary
Freescale Semiconductor, Inc.
Summary of Contents for freescale KV4 Series
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