NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 1200 / 1359

44.4.12 Status Register Extended (SPI_SREX)
The register contains status fields. The fields reflect the status of the module and indicate
the occurrence of events. This register is not writable.
Address: 4002_C000h base + 13Ch offset = 4002_C13Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
RXCTR4
0
TXCTR4
0 CMDCTR CMDNXTPTR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPI_SREX field descriptions
Field Description
31–15
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
14
RXCTR4
RX FIFO Counter[4]
This bit is an extension of SR[RXCTR]. The concatenated field {RXCTR4, RXCTR} indicates the number
of entries in the RX FIFO. This field is decremented every time the POPR is read. And this field is
incremented every time data is transferred from the shift register to the RX FIFO.
13–12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
11
TXCTR4
TX FIFO Counter[4]
This bit is an extension of SR[TXCTR]. The concatenated field {TXCTR4, TXCTR} indicates the number of
valid entries in the TX FIFO. This field is incremented every time the PUSHR is written. And this field is
decremented every time an SPI command is executed and the SPI data is transferred to the shift register.
Table continues on the next page...
Memory Map/Register Definition
KV4x Reference Manual, Rev. 2, 02/2015
1200
Preliminary
Freescale Semiconductor, Inc.