NXP Semiconductors freescale KV4 Series, Reference Manual

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Chapter 6
Clock Distribution
6.1 Introduction
The KV4x family is based on the Kinetis ARM M4 based platform and utilises the MCG
(Multiple Clock Generator) module that provides the clocks for the CPU, memories and
peripherals. The MCG has input clocks from the OSC module, providing an external feed
from a ceramic resonator/crystal/external clock, and internal RC oscillators. The MCG
has a PLL that provides a multyiplying function on the input clock source to generate
PLL clock frequencies from 90 MHz to 150 MHz and to generate PLL 2x clock
frequencies from 180 MHz to 240 MHz.
The MCG works in conjunction with the SIM module which provides optional feeds and
prescalers to the CPU, memories, and peripherals. This chip deploys the nano-edge
placement module that requires both fast peripheral clock and PLL clock or PLL 2x
clock.
The primary clocks for the system are generated from the MCGOUTCLK clock. The
clock generation circuitry provides several clock dividers that allow different portions of
the device to be clocked at different frequencies. This allows for trade-offs between
performance and power dissipation.
Various modules, such as the eFlexPWM, have module-specific clocks that can be
generated from the MCGPLLCLK clock. In addition, there are various other module-
specific clocks that have other alternate sources. Clock selection for most modules is
controlled by the SOPT registers in the SIM module.
6.2 High-level device clocking diagram
The following system oscillator , MCG , and SIM module registers control the
multiplexers, dividers, and clock gates shown in the below figure:
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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