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31.4.6 Cache Tag Storage (FMC_TAGVDW2Sn)
The 128-entry cache is a 4-way, set-associative cache with 2 sets. The ways are
numbered 0-3 and the sets are numbered 0-1. In TAGVDWxSy, x denotes the way, and y
denotes the set. This section represents tag/vld information for all sets (n=0-1) in way 2.
Address: 4001_F000h base + 110h (4d × i), where i=0d to 1d
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FMC_TAGVDW2Sn field descriptions
Field
Description
31–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19–5
cache_tag
the tag for cache entry
4–1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
valid
1-bit valid for cache entry
Chapter 31 Flash Memory Controller (FMC)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
593
Summary of Contents for freescale KV4 Series
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