NXP Semiconductors freescale KV4 Series, Reference Manual

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PWMA_SMnDISMAP0 field descriptions (continued)
Field Description
Each of the four bits of this read/write field is one-to-one associated with the four FAULTx inputs of fault
channel 0. The PWM_B output is turned off if there is a logic 1 on a FAULTx input and a 1 in the
corresponding bit of this field. A reset sets all bits in this field.
DIS0A PWM_A Fault Disable Mask 0
Each of the four bits of this read/write field is one-to-one associated with the four FAULTx inputs of fault
channel 0. The PWM_A output is turned off if there is a logic 1 on a FAULTx input and a 1 in the
corresponding bit of this field. A reset sets all bits in this field.
37.4.23 Deadtime Count Register 0 (PWMA_SMnDTCNT0)
Deadtime operation applies only to complementary channel operation. The values written
to the DTCNTx registers are in terms of IPBus clock cycles regardless of the setting of
CTRL[PRSC] and/or CTRL2[CLK_SEL]. Reset sets the deadtime count registers to a
default value of 0x07FF, selecting a deadtime of 2047 IPBus clock cycles. The DTCNTx
registers are not byte accessible.
Address: 4003_3000h base + 30h (96d × i), where i=0d to 3d
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0
DTCNT0
Write
Reset 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
PWMA_SMnDTCNT0 field descriptions
Field Description
15–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
DTCNT0 Deadtime Count Register 0
The DTCNT0 field is used to control the deadtime during 0 to 1 transitions of the PWM_A output
(assuming normal polarity).
Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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