FILT_PER x IPBus clock period). Note that even when the filter is enabled, there is a
combinational path to disable the PWM outputs. This is to ensure rapid response to
fault conditions and also to ensure fault response if the PWM module loses its clock.
The latency induced by the filter will be seen in the time to set FSTS[FFLAG] and
FSTS[FFPIN].
Address: 4003_3000h base + 190h offset = 4003_3190h
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read GSTR
Write
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWMA_FFILT field descriptions
Field
Description
15
GSTR
Fault Glitch Stretch Enable
This bit is used to enable the fault glitch stretching logic. This logic ensures that narrow fault glitches are
stretched to be at least 2 IPBus clock cycles wide. In some cases a narrow fault input can cause problems
due to the short PWM output shutdown/re-activation time. The stretching logic ensures that a glitch on the
fault input, when the fault filter is disabled, will be registered in the fault flags.
0
Fault input glitch stretching is disabled.
1
Input fault signals will be stretched to at least 2 IPBus clock cycles.
14–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10–8
FILT_CNT
Fault Filter Count
These bits represent the number of consecutive samples that must agree prior to the input filter accepting
an input transition. The number of samples is the decimal value of this field plus three: the bitfield value of
0-7 represents 3-10 samples, respectively. The value of FILT_CNT affects the input latency.
FILT_PER
Fault Filter Period
This 8-bit field applies universally to all fault inputs.
These bits represent the sampling period (in IPBus clock cycles) of the fault pin input filter. Each input is
sampled multiple times at the rate specified by this field. If FILT_PER is 0x00 (default), then the input filter
is bypassed. The value of FILT_PER affects the input latency.
NOTE: When changing values for FILT_PER from one non-zero value to another non-zero value, first
write a value of zero to clear the filter.
Memory Map and Registers
KV4x Reference Manual, Rev. 2, 02/2015
824
Preliminary
Freescale Semiconductor, Inc.
Summary of Contents for freescale KV4 Series
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