NXP Semiconductors freescale KV4 Series, Reference Manual

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23.3.12 Clear Interrupt Request Register (DMA_CINT)
The CINT provides a simple, memory-mapped mechanism to clear a given bit in the INT
to disable the interrupt request for a given channel. The given value on a register write
causes the corresponding bit in the INT to be cleared. Setting the CAIR bit provides a
global clear function, forcing the entire contents of the INT to be cleared, disabling all
DMA interrupt requests. If the NOP bit is set, the command is ignored. This allows you
to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
Address: 4000_8000h base + 1Fh offset = 4000_801Fh
Bit 7 6 5 4 3 2 1 0
Read 0 0 0
Write NOP CAIR 0 CINT
Reset 0 0 0 0 0 0 0 0
DMA_CINT field descriptions
Field Description
7
NOP
No Op enable
0 Normal operation
1 No operation, ignore the other bits in this register
6
CAIR
Clear All Interrupt Requests
0 Clear only the INT bit specified in the CINT field
1 Clear all bits in INT
5–4
Reserved
This field is reserved.
CINT Clear Interrupt Request
Clears the corresponding bit in INT
Chapter 23 Direct Memory Access Controller (eDMA)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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