NXP Semiconductors freescale KV4 Series, Reference Manual

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1
eDMA Engine
Data Path
eDMA
0
Program Model/
64
Control
n-1
To/F
rom Cr
ossbar S
witch
2
Channel Arbitration
Address Path
Read Data
Write Data
Address
Read Data
Write Data
Write Address
Int
er
nal P
er
ipher
al Bus
eDMA Peripheral
Request
eDMA Done
Transfer
Control
Descriptor (TCD)
Figure 23-290. eDMA operation, part 1
This example uses the assertion of the eDMA peripheral request signal to request service
for channel n. Channel activation via software and the TCDn_CSR[START] bit follows
the same basic flow as peripheral requests. The eDMA request input signal is registered
internally and then routed through the eDMA engine: first through the control module,
then into the program model and channel arbitration. In the next cycle, the channel
arbitration performs, using the fixed-priority or round-robin algorithm. After arbitration is
complete, the activated channel number is sent through the address path and converted
into the required address to access the local memory for TCDn. Next, the TCD memory
is accessed and the required descriptor read from the local memory and loaded into the
eDMA engine address path channel x or y registers. The TCD memory is 64 bits wide to
minimize the time needed to fetch the activated channel descriptor and load it into the
address path channel x or y registers.
The following diagram illustrates the second part of the basic data flow:
Functional description
KV4x Reference Manual, Rev. 2, 02/2015
426
Preliminary
Freescale Semiconductor, Inc.