NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 196 / 1359

SIM_CLKDIV1 field descriptions (continued)
Field Description
1000 Divide-by-9.
1001 Divide-by-10.
1010 Divide-by-11.
1011 Divide-by-12.
1100 Divide-by-13.
1101 Divide-by-14.
1110 Divide-by-15.
1111 Divide-by-16.
23–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19–16
OUTDIV4
Clock 4 output divider value
This field sets the divide value for the bus/flash clock from MCGOUTCLK. At the end of reset, it is loaded
with either 0001 or 1111 depending on FTF_FOPT[LPBOOT]. The flash clock frequency must be an
integer divide of the system clock frequency.
0000 Divide-by-1.
0001 Divide-by-2.
0010 Divide-by-3.
0011 Divide-by-4.
0100 Divide-by-5.
0101 Divide-by-6.
0110 Divide-by-7.
0111 Divide-by-8.
1000 Divide-by-9.
1001 Divide-by-10.
1010 Divide-by-11.
1011 Divide-by-12.
1100 Divide-by-13.
1101 Divide-by-14.
1110 Divide-by-15.
1111 Divide-by-16.
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
Memory map and register definition
KV4x Reference Manual, Rev. 2, 02/2015
196
Preliminary
Freescale Semiconductor, Inc.