ADC_STAT field descriptions (continued)
Field
Description
This interrupt is triggered only by the completion of a B converter scan in non-simultaneous parallel scan
modes.
0
A scan cycle has not been completed, no end of scan IRQ pending
1
A scan cycle has been completed, end of scan IRQ pending
11
EOSI0
End of Scan Interrupt
This bit indicates whether a scan of analog inputs have been completed since the last read of the status
register or since a reset. This bit is cleared by writing a one to it. This bit cannot be set by software.
STAT[EOSI0] is the preferred bit to poll for scan completion if interrupts are not enabled.
In looping scan modes, this interrupt is triggered at the completion of each iteration of the loop.
This interrupt is triggered upon the completion of any scan except for the completion of a B converter scan
in non-simultaneous parallel scan modes.
0
A scan cycle has not been completed, no end of scan IRQ pending
1
A scan cycle has been completed, end of scan IRQ pending
10
ZCI
Zero Crossing Interrupt
If the respective offset register is configured by having a value greater than 0000h, zero crossing checking
is enabled. If the offset register is programmed with 7FF8h, the result will always be less than or equal to
zero. On the other hand, if 0000h is programmed into the offset register, the result will always be greater
than or equal to zero, and no zero crossing can occur because the sign of the result will not change. This
interrupt asserts at the completion of an individual conversion which may or may not be the end of a scan.
This bit is cleared by writing a "1" to all active ZXSTAT[ZCS] bits.
0
No zero crossing interrupt request
1
Zero crossing encountered, IRQ pending if CTRL1[ZCIE] is set
9
LLMTI
Low Limit Interrupt
If the respective low limit register is enabled by having a value other than 0000h, low limit checking is
enabled. This interrupt asserts at the completion of an individual conversion which may or may not be the
end of a scan.
This bit is cleared by writing a "1" to all active LIMSTAT[LLS] bits.
0
No low limit interrupt request
1
Low limit exceeded, IRQ pending if CTRL1[LLMTIE] is set
8
HLMTI
High Limit Interrupt
If the respective high limit register is enabled by having a value other than 7FF8h, high limit checking is
enabled. This interrupt asserts at the completion of an individual conversion which may or may not be the
end of a scan.
This bit is cleared by writing a "1" to all active LIMSTAT[HLS] bits.
0
No high limit interrupt request
1
High limit exceeded, IRQ pending if CTRL1[HLMTIE] is set
UNDEFINED
This read-only bitfield is undefined and will always contain random data.
Memory Map and Registers
KV4x Reference Manual, Rev. 2, 02/2015
688
Preliminary
Freescale Semiconductor, Inc.
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