NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 462 / 1359

25.2 Introduction
The Watchdog Timer (WDOG) keeps a watch on the system functioning and resets it in
case of its failure. Reasons for failure include run-away software code and the stoppage
of the system clock that in a safety critical system can lead to serious consequences. In
such cases, the watchdog brings the system into a safe state of operation. The watchdog
monitors the operation of the system by expecting periodic communication from the
software, generally known as servicing or refreshing the watchdog. If this periodic
refreshing does not occur, the watchdog resets the system.
25.3 Features
The features of the Watchdog Timer (WDOG) include:
• Clock source input independent from CPU/bus clock. Choice between two clock
sources:
• Low-power oscillator (LPO)
• External system clock
• Unlock sequence for allowing updates to write-once WDOG control/configuration
bits.
• All WDOG control/configuration bits are writable once only within 256 bus clock
cycles of being unlocked.
• You need to always update these bits after unlocking within 256 bus clock
cycles. Failure to update these bits resets the system.
• Programmable time-out period specified in terms of number of WDOG clock cycles.
• Ability to test WDOG timer and reset with a flag indicating watchdog test.
• Quick test—Small time-out value programmed for quick test.
• Byte test—Individual bytes of timer tested one at a time.
• Read-only access to the WDOG timer—Allows dynamic check that WDOG
timer is operational.
Introduction
KV4x Reference Manual, Rev. 2, 02/2015
462
Preliminary
Freescale Semiconductor, Inc.