NXP Semiconductors freescale KV4 Series, Reference Manual

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Table 48-2. Device identification register field descriptions
Field Description
PRN Part Revision Number. Contains the revision number of the part. Value is 0x0.
DC Design Center. Indicates the design center. Value is .
PIN Part Identification Number. Contains the part number of the device. .
MIC Manufacturer Identity Code. Contains the reduced Joint Electron Device Engineering Council (JEDEC) ID.
Value is 0x00E.
IDCODE ID IDCODE Register ID. Identifies this register as the device identification register and not the bypass
register. Always set to 1.
48.3.4 Boundary scan register
The boundary scan register is connected between TDI and TDO when the EXTEST,
SAMPLE or SAMPLE/PRELOAD instructions are active. It is used to capture input pin
data, force fixed values on output pins, and select a logic value and direction for
bidirectional pins. Each bit of the boundary scan register represents a separate boundary
scan register cell, as described in the IEEE 1149.1-2001 standard and discussed in
Boundary scan . The size of the boundary scan register and bit ordering is device-
dependent and can be found in the device BSDL file.
48.4 Functional description
This section explains the JTAGC functional description.
48.4.1 JTAGC reset configuration
While in reset, the TAP controller is forced into the Test-Logic-Reset state, thus disabling
the test logic and allowing normal operation of the on-chip system logic. In addition, the
instruction register is loaded with the IDCODE instruction.
48.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port
The JTAGC block uses the IEEE 1149.1-2001 TAP for accessing registers. This port can
be shared with other TAP controllers on the MCU. Ownership of the port is determined
by the value of the currently loaded instruction.
Functional description
KV4x Reference Manual, Rev. 2, 02/2015
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Preliminary
Freescale Semiconductor, Inc.