NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 245 / 1359

The Kinetis Flashloader supports 400 kbps as the SPI baud rate.
The SPI peripheral uses the following bus attributes:
• Clock Phase = 1 (Second Edge)
• Clock Polarity = 1 (Active Low)
Because the SPI peripheral serves as a SPI slave device, each transfer should be started
by the host, and each outgoing packet should be fetched by the host.
The transfer on SPI is slightly different from I2C:
• Host will receive 1 byte after it sends out any byte.
• Received bytes should be ignored when host is sending out bytes to target
• Host starts reading bytes by sending 0x00s to target
• The byte 0x00 will be sent as response to host if target is under the following
conditions:
• Processing incoming packet
• Preparing outgoing data
• Received invalid data
The SPI bus configuration is:
• Phase = 1; data is sampled on rising edges
• Polarity = 1; idle is high
• MSB is transmitted first
For any transfer where the target does not have actual data to send, the target (slave) is
responsible for ensuring that 0x00 bytes will be returned to the host (master). The host
uses framing packets to identify real data and not "dummy" 0x00 bytes (which do not
have framing packets).
The following flowcharts demonstrate how the host reads a ping response, an ACK and a
command response from target via SPI.
Fetch
Ping response
Yes
Yes
End
Report Error
No
No
0x5A
received?
0xA7
received?
Send 0x00 to
shift out 1 byte
from target
Send 0x00 to
shift out 1 byte
from target
Send 0x00s to shift
out leftover bytes
of ping response
Figure 14-18. Host reads ping packet from target via SPI
Chapter 14 Kinetis Flashloader
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
245