NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 865 / 1359

Table 38-4. PDB1 Input Trigger Options (continued)
PDB Trigger PDB Input
0010 CMP1_out
0011 CMP2_out
0100 PIT Ch 0 Output
0101 PIT Ch 1 Output
0110 PIT Ch 2 Output
0111 PIT Ch 3 Output
1000 FTM0 initialization trigger and channel triggers, as
programmed in the FTM external trigger register (EXTTRIG)
1001 FTM1 initialization trigger and channel triggers, as
programmed in the FTM external trigger register (EXTTRIG)
1010 Reserved
1011 FTM3 initialization trigger and channel triggers, as
programmed in the FTM external trigger register (EXTTRIG)
1100 XBAR_OUT 41
1101 Reserved
1110 LPTMR Output
1111 Software Trigger
38.1.2 PDB's DAC External Trigger Input Connections
In this MCU, the following PDB's DAC external trigger inputs are implemented.
• PDB0's DAC external trigger input 0: ADCA_scan_complete
• PDB1's DAC external trigger input 0: ADCB_scan_complete
38.1.3 Pulse-Out Connection
Individual PDB Pulse-Out signals are connected to each CMP block and used for sample
window.
Chapter 38 Programmable Delay Block (PDB)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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