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41.4.16 Control 2 Register (ENC_CTRL2)
Address: 4005_5000h base + 1Eh offset = 4005_501Eh
Bit
15
14
13
12
11
10
9
8
Read
Write
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
ENC_CTRL2 field descriptions
Field
Description
15–12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
11
SABIRQ
Simultaneous PHASEA and PHASEB Change Interrupt Request
This bit indicates that the PHASEA and PHASEB inputs changed simultaneously (within a single clock
period). This event typically indicates an error condition because quadrature coding requires only one of
these inputs to change at a time. The bit remains set until it is cleared by software or a reset. Write 1 to
this bit to clear it.
0
No simultaneous change of PHASEA and PHASEB has occurred.
1
A simultaneous change of PHASEA and PHASEB has occurred.
10
SABIE
Simultaneous PHASEA and PHASEB Change Interrupt Enable
This read/write bit enables simultaneous PHASEA and PHASEB change interrupts based on SABIRQ
being set.
0
Simultaneous PHASEA and PHASEB change interrupt disabled.
1
Simultaneous PHASEA and PHASEB change interrupt enabled.
9
OUTCTL
Output Control
This bit is used to control the behavior of the POSMATCH output signal. This can control when a timer
channel captures a time stamp.
0
POSMATCH pulses when a match occurs between the position counters (POS) and the compare
value (COMP).
1
POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read.
8
REVMOD
Revolution Counter Modulus Enable
This bit is used to determine how the revolution counter (REV) is incremented/decremented. By default
REV is controlled based on the count direction and the INDEX pulse. As an option, REV can be controlled
using the roll-over/under detection during modulo counting.
0
Use INDEX pulse to increment/decrement revolution counter (REV).
1
Use modulus counting roll-over/under to increment/decrement revolution counter (REV).
Table continues on the next page...
Chapter 41 Quadrature Encoder/Decoder (ENC)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
1057
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