NXP Semiconductors freescale KV4 Series, Reference Manual

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LLWU_PF4 field descriptions (continued)
Field Description
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To
clear the flag write a one to WUF25.
0 LLWU_P25 input was not a wakeup source
1 LLWU_P25 input was a wakeup source
0
WUF24
Wakeup Flag For LLWU_P24
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To
clear the flag write a one to WUF24.
0 LLWU_P24 input was not a wakeup source
1 LLWU_P24 input was a wakeup source
19.4.14 LLWU Module Flag 5 register (LLWU_MF5)
LLWU_MF5 contains the wakeup flags indicating which internal wakeup source caused
the MCU to exit VLLS mode. For VLLS, this is the source causing the MCU reset flow.
For internal peripherals that are capable of running in a low-leakage power mode, such as
a real time clock module or CMP module, the flag from the associated peripheral is
accessible as the MWUFx bit. The flag will need to be cleared in the peripheral instead of
writing a 1 to the MWUFx bit.
NOTE
This register is reset on Chip Reset not VLLS and by reset
types that trigger Chip Reset not VLLS. It is unaffected by reset
types that do not trigger Chip Reset not VLLS. See the
Introduction details for more information.
Address: 4007_C000h base + Dh offset = 4007_C00Dh
Bit 7 6 5 4 3 2 1 0
Read MWUF7 MWUF6 MWUF5 MWUF4 MWUF3 MWUF2 MWUF1 MWUF0
Write
Reset 0 0 0 0 0 0 0 0
LLWU_MF5 field descriptions
Field Description
7
MWUF7
Wakeup flag For module 7
Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear
the flag, follow the internal peripheral flag clearing mechanism.
Table continues on the next page...
Memory map/register definition
KV4x Reference Manual, Rev. 2, 02/2015
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Preliminary
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