NXP Semiconductors freescale KV4 Series, Reference Manual

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PDB counter
Ch n pre-trigger 0
Ch n pre-trigger 1
CH n DLY1
CH n DLY0
SC[LDOK]
Figure 38-83. Registers update with SC[LDMOD] = x1
38.5.6 Interrupts
PDB can generate two interrupts: PDB interrupt and PDB sequence error interrupt. The
following table summarizes the interrupts.
Table 38-89. PDB interrupt summary
Interrupt Flags Enable bit
PDB Interrupt SC[PDBIF] SC[PDBIE] = 1 and
SC[DMAEN] = 0
PDB Sequence Error Interrupt CH n S[ERR m ] SC[PDBEIE] = 1
38.5.7 DMA
If SC[DMAEN] is set, PDB can generate a DMA transfer request when SC[PDBIF] is
set. When DMA is enabled, the PDB interrupt is not issued.
38.6 Application information
38.6.1 Impact of using the prescaler and multiplication factor on
timing resolution
Use of prescaler and multiplication factor greater than 1 limits the count/delay accuracy
in terms of peripheral clock cycles (to the modulus of the prescaler X multiplication
factor). If the multiplication factor is set to 1 and the prescaler is set to 2 then the only
Chapter 38 Programmable Delay Block (PDB)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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