NXP Semiconductors freescale KV4 Series, Reference Manual

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Any bus access to a peripheral that has its clock disabled generates an error termination.
6.5 Module clocks
The following table summarizes the clocks associated with each module.
Table 6-1. Module clocks
Module Bus interface clock Internal clocks I/O interface clocks
Core modules
ARM Cortex-M4 core Core/System clock Core clock —
NVIC Core/System clock — —
DAP Core/System clock — —
ITM Core/System clock — —
cJTAG, JTAGC — — JTAG_CLK
System modules
DMA Core/System clock — —
DMA Mux Bus / Flash clock — —
Port control Bus / Flash clock LPO —
Crossbar Switch Core/System clock — —
Peripheral bridges Core/System clock Bus clock, Flash clock —
XBARA,XBARB,AOI Bus / Flash clock —
LLWU, PMC, SIM, RCM Bus/ Flash clock LPO —
Mode controller Bus / Flash clock — —
MCM Core/System clock — —
EWM Bus / Flash clock LPO —
Watchdog timer Bus / Flash clock LPO —
Clocks
MCG Bus /Flash clock MCGOUTCLK, MCGPLLCLK,
MCGFLLCLK, MCGIRCLK,
OSCERCLK,
OSCERCLK_UNDIV
—
OSC Bus / Flash clock OSCERCLK,
OSCERCLK_UNDIV
—
Memory and memory interfaces
Flash Controller Core/System clock Flash clock —
Flash memory Bus /Flash clock — —
nanoedge module Fast Peripheral clock +
MCGPLLCLK or
MCGPLL2XCLK
— —
Security
CRC Core/System clock — —
Analog
Table continues on the next page...
Module clocks
KV4x Reference Manual, Rev. 2, 02/2015
100
Preliminary
Freescale Semiconductor, Inc.