NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 1082 / 1359

43.3.2 CAN Tx
This pin is the transmit pin to the CAN bus transceiver. Dominant state is represented by
logic level 0. Recessive state is represented by logic level 1.
43.4 Memory map/register definition
This section describes the registers and data structures in the FlexCAN module. The base
address of the module depends on the particular memory map of the MCU.
43.4.1 FlexCAN memory mapping
The memory map for the FlexCAN module is shown in the following table.
The address space occupied by FlexCAN has 128 bytes for registers starting at the
module base address, followed by embedded RAM starting at address 0x0080.
Each individual register is identified by its complete name and the corresponding
mnemonic. The access type can be Supervisor (S) or Unrestricted (U). Most of the
registers can be configured to have either Supervisor or Unrestricted access by
programming the SUPV field in the MCR register. These registers are identified as S/U
in the Access column of
Table 43-2 .
Table 43-2. Register access and reset information
Register Access type
Affected by
hard reset
Affected by
soft reset
Module Configuration Register (MCR) S Yes Yes
Control 1 register (CTRL1) S/U Yes No
Free Running Timer register (TIMER) S/U Yes Yes
Rx Mailboxes Global Mask register (RXMGMASK) S/U No No
Rx Buffer 14 Mask register (RX14MASK) S/U No No
Rx Buffer 15 Mask register (RX15MASK) S/U No No
Error Counter Register (ECR) S/U Yes Yes
Error and Status 1 Register (ESR1) S/U Yes Yes
Interrupt Masks 1 register (IMASK1) S/U Yes Yes
Interrupt Flags 1 register (IFLAG1) S/U Yes Yes
Control 2 Register (CTRL2) S/U Yes No
Error and Status 2 Register (ESR2) S/U Yes Yes
CRC Register (CRCR) S/U Yes Yes
Table continues on the next page...
Memory map/register definition
KV4x Reference Manual, Rev. 2, 02/2015
1082
Preliminary
Freescale Semiconductor, Inc.