NXP Semiconductors freescale KV4 Series, Reference Manual

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9.3 Debug Port Pin Descriptions
The debug port pins default after POR to their JTAG functionality with the exception of
JTAG_TRST_b and can be later reassigned to their alternate functionalities. In cJTAG
and SWD modes JTAG_TDI and JTAG_TRST_b can be configured to alternate GPIO
functions.
Table 9-2. Debug port pins
Pin Name JTAG Debug Port cJTAG Debug Port SWD Debug Port Internal Pull-
up\Down
Type Description Type Description Type Description
JTAG_TMS I/O JTAG Test
Mode
Selection I/O cJTAG Data I/O Serial Wire
Data Pull-up
JTAG_TCLK I JTAG Test
Clock I cJTAG Clock I Serial Wire
Clock Pull-down
JTAG_TDI I JTAG Test
Data Input - - - - Pull-up
JTAG_TDO/
TRACE_SWO O JTAG Test
Data Output O Trace output
over a single
pin O Trace output
over a single
pin N/C
JTAG_TRST_
b I JTAG Reset I cJTAG Reset - - Pull-up
9.4 JTAG status and control registers
Through the ARM Debug Access Port (DAP), the debugger has access to the status and
control elements, implemented as registers on the DAP bus as shown in the following
figure. These registers provide additional control and status for low power mode recovery
and typical run-control scenarios. The status register bits also provide a means for the
debugger to get updated status of the core without having to initiate a bus transaction
across the crossbar switch, thus remaining less intrusive during a debug session.
It is important to note that these DAP control and status registers are not memory mapped
within the system memory map and are only accessible via the Debug Access Port (DAP)
using JTAG or cJTAG. The MDM-AP is accessible as Debug Access Port 1 with the
available registers shown in the table below.
Table 9-3. MDM-AP Register Summary
Address Register Description
Table continues on the next page...
Debug Port Pin Descriptions
KV4x Reference Manual, Rev. 2, 02/2015
120
Preliminary
Freescale Semiconductor, Inc.