NXP Semiconductors freescale KV4 Series, Reference Manual

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Table 23-295. eDMA peak request rate (MReq/sec)
System frequency (MHz)
Request rate
with zero wait states
Request rate
with wait states
66.6 7.4 5.8
83.3 9.2 7.2
100.0 11.1 8.7
133.3 14.8 11.6
150.0 16.6 13.0
A general formula to compute the peak request rate with overlapping requests is:
PEAKreq = freq / [ entry + (1 + read_ws) + (1 + write_ws) + exit ]
where:
Table 23-296. Peak request formula operands
Operand Description
PEAKreq Peak request rate
freq System frequency
entry Channel startup (4 cycles)
read_ws Wait states seen during the system bus read data phase
write_ws Wait states seen during the system bus write data phase
exit Channel shutdown (3 cycles)
23.4.4.3 eDMA performance example
Consider a system with the following characteristics:
• Internal SRAM can be accessed with one wait-state when viewed from the system
bus data phase
• All internal peripheral bus reads require two wait-states, and internal peripheral bus
writes three wait-states viewed from the system bus data phase
• System operates at 150 MHz
For an SRAM to internal peripheral bus transfer,
PEAKreq = 150 MHz / [ 4 + (1 + 1) + (1 + 3) + 3 ] cycles = 11.5 Mreq/sec
For an internal peripheral bus to SRAM transfer,
Functional description
KV4x Reference Manual, Rev. 2, 02/2015
434
Preliminary
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