NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 1018 / 1359

phase A
phase B
FTM counter
MOD
CNTIN
0x0000
Time
Figure 39-259. Motor position jittering near maximum and minimum count value
The first highlighted transition causes a jitter on the FTM counter value near the
maximum count value (MOD). The second indicated transition occurs on phase A and
causes the FTM counter transition between the maximum and minimum count values
which are defined by MOD and CNTIN registers.
The appropriate settings of the phase A and phase B input filters are important to avoid
glitches that may cause oscillation on the FTM counter value. The preceding figures
show examples of oscillations that can be caused by poor input filter setup. Thus, it is
important to guarantee a minimum pulse width to avoid these oscillations.
39.5.26 BDM mode
When the chip is in BDM mode, the BDMMODE[1:0] bits select the behavior of the
FTM counter, the CH(n)F bit, the channels output, and the writes to the MOD, CNTIN,
and C(n)V registers according to the following table.
Table 39-254. FTM behavior when the chip Is in BDM mode
BDMMODE
FTM
Counter
CH(n)F Bit FTM Channels Output Writes to MOD, CNTIN, and C(n)V Registers
00 Stopped can be set Functional mode Writes to these registers bypass the registers
buffers
01 Stopped is not set The channels outputs are forced
to their safe value according to
POLn bit Writes to these registers bypass the registers
buffers
10 Stopped is not set The channels outputs are frozen
when the chip enters in BDM
mode Writes to these registers bypass the registers
buffers
Table continues on the next page...
Functional description
KV4x Reference Manual, Rev. 2, 02/2015
1018
Preliminary
Freescale Semiconductor, Inc.