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When DMA support is enabled by setting SCR[DMAEN] and the interrupt is enabled by
setting SCR[IER], SCR[IEF], or both, the corresponding change on COUT forces a DMA
transfer request to wake up the system from STOP modes. After the data transfer has
finished, system will go back to STOP modes. Refer to DMA chapters in the device
reference manual for the asynchronous DMA function for details.
35.8 Digital-to-analog converter
The figure found here shows the block diagram of the DAC module.
It contains a 64-tap resistor ladder network and a 64-to-1 multiplexer, which selects an
output voltage from one of 64 distinct levels that outputs from DACO. It is controlled
through the DAC Control Register (DACCR). Its supply reference source can be selected
from two sources V
in1
and V
in2
. The module can be powered down or disabled when not
in use. When in Disabled mode, DACO is connected to the analog ground.
VOSEL[5:0]
DACO
MUX
MUX
DACEN
Vin
VRSEL
V
in1
V
in2
Figure 35-42. 6-bit DAC block diagram
35.9 DAC functional description
This section provides DAC functional description information.
Chapter 35 Comparator (CMP)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
751
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